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News Story Source: https://www.nextbigfuture.com by Brian Wang
TSMC was the first company to use ASML's EUV lithography machines for high-volume production and now has at least three processes that use EUV for select layers. They use EUV lithography for its N7+, N6, and N5 nodes.
TSMC's 2nd generation 7 nm technology (N7+) uses EUV for up to four layers in order to reduce its use of multi-patterning techniques when building highly complex circuits. The 6 nm process (N6) is for customers to re-use IP designed for 1st generation 7 nm, per the report. TSMC's 5 nm process (N5) can use EUV for up to 14 layers. 5nm has significant increase in transistor density and performance enhancements.
2nd generation 5 nm (N5P) and 4 nm (N4) fabrication processes are based 5 nm technology and will have performance and power benefits. N5P will be available in 2021. N4 chips will have volume production in 2022.
Next-generation 3 nm process (N3) will be a full node improvement over N5. N3 will have 70 percent logic density gain, 15-percent perform
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